CMOS LC Voltage-Controlled Oscillator Sizing through Particle Swarm Optimization (PSO)

This paper introduces an advanced design methodology of a 2.6 GHz CMOS LC Voltage-Controlled Oscillator (VCO) within the AMS CMOS 0.35 μm technology process. The primary objectives of this design approach are to achieve minimal power consumption, a high figure-of-merit (FOM), and low phase noise. In addressing the inherent design challenges, a metaheuristic Particle Swarm Optimization (PSO) is implemented to identify the most effective dimensions for the components of the LC-VCO. In particular, the PSO algorithm is applied to optimize the channel length and width of the MOS transistors, aiming to minimize the VCO’s phase noise while adhering to predefined constraints. The proposed design is thoroughly simulated using the ADS Tool, demonstrating promising results. The optimized LC-VCO achieves a phase noise of -125.35 dBc/Hz at a 1 MHz offset frequency from a carrier frequency operating at 2.6 GHz, with a power consumption of 9 mW. To emphasize the efficacy of the proposed design, a comparative analysis with previously published works is in-cluded. This comparison serves to underscore the superior performance achieved through the pre-sented optimization methodology.